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| LTC3865/LTC3865-1 3865f typical a pplica t ion descrip t ion dual, 2-phase synchronous dc/dc controller with pin selectable outputs the ltc ? 3865/LTC3865-1 are high performance dual synchronous step-down dc/dc switching regulator controllers that drive all n - channel synchronous power mosfet stages. a constant frequency current mode architecture allows a phase-lockable frequency of up to 770khz. power loss and noise are minimized by operating the two controller output stages out of phase. opti-loop ? compensation allows the transient response to be optimized over a wide range of output capacitance and esr values. independent track/soft-start pins for each controller ramp the output voltage during start-up. current foldback limits mosfet heat dissipation during short-circuit conditions. the mode/pllin pin selects among burst mode ? operation, pulse-skipping mode, and continuous inductor current mode. the output volt- ages can be precisely programmed by pin strapping or external resistors. the LTC3865/LTC3865-1 are available in low profle (5mm 5mm) 32-pin qfn and 38-lead thermally enhanced tssop packages. fea t ures a pplica t ions n dual, 180 phased controllers n 2-pin vid output voltage programming from 0.6v to 5v n high effciency: up to 95% n r sense or dcr current sensing n phase-lockable fixed frequency 250khz to 770khz n adjustable current limit n dual n-channel mosfet synchronous drive n wide v in range: 4.5v to 38v operation n adjustable soft-start current ramping or tracking n output ov protection with reverse current limit n power good output voltage monitor n 32-pin 5mm 5mm qfn and 38-lead tssop packages n dc power distribution systems high effciency 1.5v/15a, 1.2v/15a step-down converter 0.1f 0.47h 1000pf 1000pf 1000pf 22f 50v 10k v out1 1.5v 15a 0.1f 0.47h 1000pf 100f 15k 162k v out2 1.2v 15a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + sense1 ? sense2 ? v osense1 v osense2 i th1 i th2 v in intv cc tk/ss1 tk/ss2 v in 4.5v to 24v 3865 ta01a 0.1f 100pf 0.1f LTC3865 vid11 vid12 vid21 vid22 4.7f 100f c out2,3 100pf 100 100 100 100 2.2 1f 2m 2m + c out5,6 + + load current (a) 30 efficiency (%) power loss (w) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3865 ta01b 0 0.1 10 1 0.01 0.1 v in = 12v v out = 1.5v efficiency power loss effciency and power loss vs load current l , lt, ltc, ltm, burst mode, opti-loop, module, linear technology and the linear logo are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. u.s. patents, including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258.
LTC3865/LTC3865-1 3865f input supply voltage (v in ) ......................... C0.3v to 40v topside driver voltages boost1, boost2 .................................. C0.3v to 46v switch voltage (sw1, sw2) ......................... C5v to 40v intv cc , run1, run2, pgood(s), extv cc , (boost1-sw1), (boost2-sw2) ................. C0.3v to 6v sense1 + , sense2 + , sense1 C , sense2 C v osense1 , v osense2 voltages .................... C0.3v to 5.8v mode/pllin, i lim , tk/ss1, tk/ss2, vid11, vid12, vid21, vid22, freq voltages ... C0.3v to intv cc (note 1) a bsolu t e maxi m u m r a t ings LTC3865 LTC3865 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 sgnd uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v osense1 tk/ss1 i th1 vid11 vid12 i th2 tk/ss2 v osense2 boost1 bg1 v in intv cc extv cc bg2 pgnd boost2 sense1 ? sense1 + run1 freq vid22 mode/pllin sw1 tg1 sense2 ? sense2 + run2 vid21 i lim pgood sw2 tg2 t jmax = 125c, q ja = 34c/w, q jc = 3c/w exposed pad (pin 33) is sgnd, must be soldered to pcb 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 top view fe package 38-lead plastic tssop 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 run1 sense1 + sense ? nc v osense1 tk/ss1 i th1 sgnd vid11 vid12 i th2 tk/ss2 v osense2 nc sense2 ? sense2 + run2 vid21 i lim freq vid22 mode/pllin sw1 tg1 boost1 pgnd1 bg1 v in intv cc extv cc bg2 pgnd2 boost2 nc tg2 sw2 pgood1 pgood2 39 sgnd t jmax = 125c, q ja = 28c/w exposed pad (pin 39) is sgnd, must be soldered to pcb p in c on f igura t ion i th1 , i th2 voltages .................................... C0.3v to 2.7v intv cc dc output current .....................................80ma operating junction temperature range (notes 2, 3) LTC3865/LTC3865-1 .......................... C40c to 125c storage temperature range ................... C65c to 125c lead temperature (soldering, 10 sec) fe package ....................................................... 300c LTC3865/LTC3865-1 3865f o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LTC3865euh#pbf LTC3865euh#trpbf 3865 32-lead (5mm 5mm) plastic qfn C40c to 85c LTC3865euh-1#pbf LTC3865euh-1#trpbf 38651 32-lead (5mm 5mm) plastic qfn C40c to 85c LTC3865iuh#pbf LTC3865iuh#trpbf 3865 32-lead (5mm 5mm) plastic qfn C40c to 125c LTC3865iuh-1#pbf LTC3865iuh-1#trpbf 38651 32-lead (5mm 5mm) plastic qfn C40c to 125c LTC3865efe#pbf LTC3865efe#trpbf LTC3865fe 38-lead plastic tssop C40c to 85c LTC3865ife#pbf LTC3865ife#trpbf LTC3865fe 38-lead plastic tssop C40c to 125c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ p in c on f igura t ion LTC3865-1 32 31 30 29 28 27 26 25 9 10 11 12 top view 33 sgnd uh package 32-lead (5mm s 5mm) plastic qfn 13 14 15 16 17 18 19 20 21 22 23 24 8 7 6 5 4 3 2 1 v osense1 tk/ss1 i th1 vid11 vid12 i th2 tk/ss2 v osense2 boost1 bg1 v in intv cc extv cc bg2 pgnd boost2 sense1 ? sense1 + run1 freq vid22 mode/pllin sw1 tg1 sense2 ? sense2 + run2 vid21 pgood2 pgood1 sw2 tg2 t jmax = 125c, ja = 34c/w, jc = 3c/w exposed pad (pin 33) is sgnd, must be soldered to pcb LTC3865/LTC3865-1 3865f e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t j = 25c. v in = 15v, v run1,2 = 5v unless otherwise noted. symbol parameter conditions min typ max units main control loops v in input voltage 4.5 38 v v osense1,2 output voltage sensing (e-grade) (note 4) i th1,2 voltage = 1.2v vid11 = vid21 = gnd, vid12 = vid22 = gnd vid11 = vid21 = gnd, vid12 = vid22 = float vid11 = vid21 = gnd, vid12 = vid22 = intv cc vid11 = vid21 = float, vid12 = vid22 = gnd vid11 = vid21 = float, vid12 = vid22 = float vid11 = vid21 = float, vid12 = vid22 = intv cc vid11 = vid21 = intv cc , vid12 = vid22 = gnd vid11 = vid21 = intv cc , vid12 = vid22 = float vid11 = vid21 = intv cc , vid12 = vid22 = intv cc l l l l l l l l l 1.089 0.990 1.188 1.485 0.596 1.782 2.463 3.251 4.925 1.100 1.000 1.200 1.500 0.602 1.800 2.500 3.300 5.000 1.111 1.010 1.212 1.515 0.608 1.818 2.538 3.350 5.075 v v v v v v v v v output voltage sensing (i-grade) (note 4) i th1,2 voltage = 1.2v vid11 = vid21 = gnd, vid12 = vid22 = gnd vid11 = vid21 = gnd, vid12 = vid22 = float vid11 = vid21 = gnd, vid12 = vid22 = intv cc vid11 = vid21 = float, vid12 = vid22 = gnd vid11 = vid21 = float, vid12 = vid22 = float vid11 = vid21 = float, vid12 = vid22 = intv cc vid11 = vid21 = intv cc , vid12 = vid22 = gnd vid11 = vid21 = intv cc , vid12 = vid22 = float vid11 = vid21 = intv cc , vid12 = vid22 = intv cc l l l l l l l l l 1.084 0.985 1.182 1.478 0.593 1.773 2.450 3.234 4.900 1.100 1.000 1.200 1.500 0.602 1.800 2.500 3.300 5.000 1.117 1.015 1.218 1.523 0.611 1.827 2.550 3.366 5.100 v v v v v v v v v i osense1,2 feedback current (note 4) vid11 = vid21 = vid12 = vid22 = float C10 C50 na v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 4) 0.002 0.02 %/v v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v measured in servo loop; ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m1,2 transconductance amplifer g m i th1,2 = 1.2v; sink/source 5a; (note 4) 2.2 mmho i q input dc supply current normal mode shutdown (note 5) v in = 15v v run1,2 = 0v 3 30 50 ma a uvlo undervoltage lockout on intv cc v intvcc ramping down 3.3 v uvlo hys uvlo hysteresis 0.55 v v ovl feedback overvoltage lockout measured at v osense1,2 with vid pins floating l 0.64 0.66 0.68 v i sense sense pins total current (each channel); v sense1,2 = 3.3v 1 2 a df max maximum duty cycle in dropout 94 95 % i tk/ss1,2 soft-start charge current v tk/ss1,2 = 0v 0.9 1.3 1.7 a v run1,2 run pin on threshold v run1 , v run2 rising l 1.1 1.22 1.35 v v run1,2hys run pin on hysteresis 80 mv i run1,2hys run pin current hysteresis 4.5 a v sense(max) maximum current sense threshold (e-grade) v ith1,2 = 3.3v, i lim = 0v v ith1,2 = 3.3v, i lim = float v ith1,2 = 3.3v, i lim = intv cc in overvoltage condition l l l l 24 44 68 C63 30 50 75 C53 36 56 82 C43 mv mv mv mv maximum current sense threshold (i-grade) v ith1,2 = 3.3v, i lim = 0v v ith1,2 = 3.3v, i lim = float v ith1,2 = 3.3v, i lim = intv cc in overvoltage condition l l l l 22 42 66 C65 30 50 75 C53 38 58 84 C41 v v v v tg r up tg driver pull-up on-resistance tg high 2.6 tg r down tg driver pull-down on-resistance tg low 1.5 bg r up bg driver pull-up on-resistance bg high 3 LTC3865/LTC3865-1 3865f note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LTC3865e/LTC3865e-1 are guaranteed to meet performance specifcations over the 0c to 85c operating junction temperature range. specifcations over the C40c to 85c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the LTC3865i/LTC3865i-1 are guaranteed to meet performance specifcations over the full C40c to 125c operating junction temperature range. note that the maximum ambient temperature is determined by specifc operating conditions in conjunction with board layout, the rated package thermal resistance and other environmental factors. note 3: t j is calculated from the ambient temperature t a and power dissipation p d according to the following formulas: LTC3865uh: t j = t a + (p d ? 34c/w) LTC3865fe: t j = t a + (p d ? 25c/w) note 4: the LTC3865/LTC3865-1 are tested in a feedback loop that servos v ith1,2 to a specifed voltage and measures the resultant v osense1,2 . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specifed for an inductor peak- to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 8: v sense(max) defaults to 50mv for the LTC3865-1. e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating junction temperature range, otherwise specifcations are at t j = 25c. v in = 15v, v run1,2 = 5v unless otherwise noted. symbol parameter conditions min typ max units bg r down bg driver pull-down on-resistance bg low 1.4 tg1,2 t r tg1,2 t f tg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg1,2 t r bg1,2 t f bg transition time: rise time fall time (note 6) c load = 3300pf c load = 3300pf 25 25 ns ns tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay top switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 4.8 5.0 5.2 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5v 50 100 mv v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency r freq = 162k 450 500 550 khz f low lowest frequency r freq = 0 210 250 290 khz f high highest frequency r freq 325k 650 770 880 khz r mode/pllin mode/pllin input resistance 250 k? i freq frequency setting current 6.5 7.5 8.5 a pgood output v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5v 2 a v pg pgood trip level v osense with respect to set regulated voltage vid11 = vid12 = vid21 = vid22 = float v osense ramping negative v osense ramping postitive C7 7 C10 10 C12.5 12.5 % % t pg pgood bad blanking time measured from vid transitition edge 100 s LTC3865/LTC3865-1 3865f load step (burst mode operation) load step (forced continuous mode) load step (pulse-skipping mode) inductor current at light load prebiased output at 1v coincident tracking v out 100mv/div ac- coupled i load 5a/div 500ma to 7a i l 5a/div 40s/div v in = 12v v out = 1.5v figure 16 circuit 3865 g01 v out 100mv/div ac- coupled i load 5a/div 500ma to 7a i l 5a/div 40s/div 3865 g02 v in = 12v v out = 1.5v figure 16 circuit v out 100mv/div ac- coupled i load 5a/div 500ma to 7a i l 5a/div 40s/div 3865 g03 v in = 12v v out = 1.5v figure 16 circuit run 2v/div v track/ss 1v/div v out = 1.5v 500mv/div 40ms/div 3865 g05 forced continuous mode 5a/div pulse- skipping mode 5a/div burst mode operation 5a/div 2s/div v in = 12v v out = 1.5v i load = 100ma figure 16 circuit 3865 g04 run1 2v/div 40ms/div 3865 g06 v out2 = 1.2v 1 load 500mv/div v out1 = 1.5v 1 load 500mv/div typical p er f or m ance c harac t eris t ics effciency vs load current effciency vs load current effciency and power loss vs input voltage load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3865 g23 0 0.1 v in = 12v v out = 1.5v figure 16 circuit burst dcm ccm load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3865 g24 0 0.1 v in = 12v v out = 1.2v figure 16 circuit burst dcm ccm input voltage (v) 0 efficiency (%) power loss (w) 50 60 70 3865 g25 40 30 20 10 20 80 90 100 3 2 1 0 4 5 30 efficiency power loss figure 16 circuit LTC3865/LTC3865-1 3865f typical p er f or m ance c harac t eris t ics current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage maximum current sense threshold vs duty cycle tk/ss pull-up current vs temperature tracking up and down with external ramp (forced continuous mode) quiescent current vs input voltage without extv cc intv cc line regulation maximum current sense voltage vs feedback voltage (current foldback) v ith (v) 0 ?40 v sense (mv) ?20 0 20 40 60 80 0.5 1 1.5 2 3865 g10 i lim = intv cc i lim = gnd i lim = float v sense common mode voltage (v) 0 current sense threshold (mv) 30 40 50 3 5 20 10 0 1 2 4 60 70 80 3865 g11 i lim = intv cc i lim = gnd i lim = float 60 80 100 40 20 50 70 90 30 10 0 duty cycle (%) 0 current sense threshold (mv) 60 100 20 40 80 3865 g12 i lim = intv cc i lim = gnd i lim = float tk/ss1 tk/ss2 2v/div v out1 = 1.5v 1 load 500mv/div v out2 = 1.2v 1 load 500mv/div 20ms/div 3865 g07 input voltage (v) 0 intv cc voltage (v) 4.25 4.50 4.75 40 3865 g09 4.00 3.50 3.75 3.00 10 20 30 5 15 25 35 3.25 5.25 5.00 feedback voltage (v) 0 0 maximum current sense voltage (mv) 20 40 60 0.1 0.2 0.3 0.4 3865 g13 0.5 80 100 10 30 50 70 90 0.6 i lim = intv cc i lim = float i lim = gnd temperature (c) ?50 tk/ss current (a) 1.75 25 3865 g14 1.00 0.50 ?25 0 50 0.25 0 2.00 1.50 1.25 0.75 75 100 125 input voltage (v) 5 10 0 quiescent current (ma) 2 5 15 25 30 3865 g08 1 4 3 20 35 40 v in = 15v LTC3865/LTC3865-1 3865f typical p er f or m ance c harac t eris t ics undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs input voltage shutdown current vs temperature quiescent current vs temperature without extv cc temperature (c) ?50 ?25 0 intv cc voltage (v) 2 5 0 50 75 3865 g18 1 4 3 25 100 125 falling rising input voltage (v) 4 450 frequency (khz) 470 490 510 10 16 22 28 3865 g19 34 530 550 460 480 500 520 540 40 input voltage (v) 0 5 0 input current (a) 20 50 10 20 25 3865 g20 10 40 30 15 30 35 40 temperature (c) ?50 ?25 0 quiescent current (ma) 2 5 0 50 75 3865 g22 1 4 3 25 100 125 v in = 15v temperature (c) ?50 ?25 0 shutdown current (a) 20 50 0 50 75 3865 g21 10 40 30 25 100 125 v in = 15v regulated feedback voltage vs temperature oscillator frequency vs temperature temperature (c) ?50 100 oscillator frequency (khz) 200 400 500 600 50 1000 3865 g17 300 0 ?25 75 100 25 125 700 800 900 v freq = intv cc v freq = 1.2v v freq = 0v temperature (c) ?50 regulated feedback voltage (v) 0.604 0.606 0.608 25 75 3865 g16 0.602 0.600 ?25 0 50 100 125 0.598 0.596 shutdown (run) threshold vs temperature temperature (c) ?50 ?25 1.0 run pin voltage (v) 1.2 1.5 0 50 75 3865 g15 1.1 1.4 1.3 25 100 125 off on LTC3865/LTC3865-1 3865f p in func t ions (qfn/tssop) v osense1 , v osense2 (pins 1, 8/pins 5, 13): when the internal programmable resistive divider is used, these pins must be connected to their corresponding outputs. when an external resistive divider is used, these pins are used for error amplifer feedback inputs. they receive the remotely sensed feedback voltages for each channel directly from the outputs or from the external divider across the outputs. tk/ss1, tk/ss2 (pins 2, 7/pins 6, 12): output voltage tracking and soft-start inputs. when one channel is confgured to be master of the two channels, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when a channel is confgured to be the slave of the two channels, the output voltage ramp of the master channel can be reproduced by a re- sistor divider and applied to this pin of the slave channel. internal soft-start currents of 1.3a charge the soft-start capacitors. i th1 , i th2 (pins 3, 6/pins 7, 11): current control thresholds and error amplifer compensation points. each associated channels current comparator tripping threshold increases with its i th control voltage. vid11, vid12, vid21, vid22 (pins 4, 5, 12, 28/ pins 9, 10, 18, 37): vid inputs for output voltage programming. tie these pins to intv cc , gnd or leave them foating to set the output voltages. i lim (pin 13/pin 19) (LTC3865 only): current compara- tor sense voltage range inputs. this pin can be tied to sgnd, float or intv cc to set the maximum current sense threshold for each comparator. current compara- tor sense voltage range of the LTC3865-1 is set to default value of 50mv. pgood (pin 14 LTC3865/na): co-bonded power good indicator output for LTC3865 in qfn package. open-drain logic output that is pulled to ground when either channel output exceeds 10% regulation window, after the internal 20s power bad mask timer expires. pgood1, pgood2 (pins 14, 13 LTC3865-1/pins 21, 20): separate power good indicator outputs for LTC3865-1 in qfn package and LTC3865 in fe package. open-drain logic output that is pulled to ground when the corresponding channel output exceeds 10% regulation window, after the internal 20s power bad mask timer expires. pgnd (pin 18/na): power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets, the (C) terminal of c vcc and the (C) terminal of c in . extv cc (pin 20/pin 28): external power input to an inter- nal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7v. do not exceed 6v on this pin. intv cc (pin 21/pin 29): internal 5v regulator output. the control circuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7f low esr tan- talum or ceramic capacitor. v in (pin 22/pin 30): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). bg1, bg2 (pins 23, 19/pin 31, 27): bottom gate driver outputs. these pins drive the gates of the bottom n-chan- nel mosfets between pgnd and intv cc . boost1, boost2 (pins 24, 17/pins 33, 25): boosted floating driver supplies. the (+) terminal of the booststrap capacitors connect to these pins. these pins swing from a diode voltage drop below intv cc up to v in + intv cc . tg1, tg2 (pins 25, 16/pins 34, 23): top gate driver outputs. these are the outputs of foating drivers with a voltage swing equal to intv cc superimposed on the switch nodes voltages. sw1, sw2 (pins 26, 15/pins 35, 22): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . LTC3865/LTC3865-1 0 3865f mode/pllin (pin 27/pin 36): force continuous mode, burst mode or pulse-skip mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force both channels in continuous mode of operation. connect to intv cc to enable pulse-skip mode of operation. leaving the pin foating will enable burst mode operation. a clock on the pin will force the controller into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. freq (pin 29/pin 38): this pin sets the frequency of the internal oscillator. a constant current of 7.5a is fowing out of this pin and a resistor connected to this pin sets its dc voltage, which in turn, sets the frequency of the internal oscillator. run1, run2 (pins 30, 11/pins 1, 17): run control inputs. a voltage above 1.2v on either pin turns on the ic. however, forcing either of these pins below 1.2v causes the ic to shut down the circuitry required for that particular channel. there are 1a pull-up currents for these pins. once the run pin rises above 1.2v, an additional 4.5a pull-up current is added to the pin. p in func t ions (qfn/tssop) sense1 + , sense2 + (pins 31, 10/pins 2, 16): current sense comparator inputs. the (+) inputs to the current comparators are normally connected to dcr sensing networks or current sensing resistors. sense1 C , sense2 C (pins 32, 9/pin 3, 15): current sense comparator inputs. the (C) inputs to the current compara- tors are connected to the outputs. sgnd (pin 33/pin 8): signal ground. all small-signal components and compensation components should connect to this ground, which in turn connects to pgnd at one point. pin 33 is the exposed pad and available for qfn package. sgnd (exposed pad pin 33/ exposed pad pin 39): signal ground. must be soldered to pcb, providing a local ground for the control components of the ic, and be tied to the pgnd pin under the ic. pgnd1, pgnd2 (na/pins 32, 26): power ground pin. connect this pin closely to the sources of the bottom n-channel mosfets, the (C) terminal of c vcc and the (C) terminal of c in . LTC3865/LTC3865-1 3865f f unc t ional diagra m 4.7v ? + ? + ? + v in 1 a slope compensation uvlo slope recovery active clamp osc s r q 3k run switch logic and anti- shoot through bg on fcnt 0.6v ov 1.2v 0.5v i th r c intv cc intv cc i lim i cmp c c1 ss sgnd 0.66v v fb run pgnd pgood intv cc extv cc i rev sw tg c b v in c in v in sleep boost bursten ? + ? + uv ov c vcc v out c out m2 m1 l1 d b mode/pllin sense + sense ? ? + 0.6v ref tk/ss run 0.55v ? + freq/freq 7.5a pll-sync and lpf mode/sync detect + 5v reg 1.3 a c ss + v osense ? + ? + f f 0.54v vid1 vid2 3865 fbd 1 51k i thb ? + ea + input vid logic and resistive dividers LTC3865/LTC3865-1 3865f o pera t ion main control loop the LTC3865/LTC3865-1 are constant-frequency, current mode step-down controllers with two channels operating 180 degrees out-of-phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the rs latch, and turned off when the main current comparator, i cmp , resets the rs latch. the peak inductor current at which i cmp resets the rs latch is controlled by the voltage on the i th pin, which is the output of each error amplifer, ea (refer to the functional diagram). v fb is the voltage feedback signal, which is compared to the internal reference voltage by the ea. when the load current increas- es, it causes a slight decrease in feedback voltage relative to the 0.6v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor cur- rent starts to reverse, as indicated by the reverse current comparator i rev , or the beginning of the next cycle. intv cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.7v, an internal 5v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7v, the 5v regulator is turned off and an internal switch is turned on connecting extv cc . using the extv cc pin allows the intv cc power to be derived from a high effciency external source such as one of the LTC3865/LTC3865-1 switching regulator outputs. each top mosfet driver is biased from the foating boot- strap capacitor, c b , which normally recharges during each off cycle through an external diode when the top mosfet turns off. if the input voltage v in decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period every third cycle to allow c b to recharge. however, it is recommended that a load be present during the drop-out transition to ensure c b is recharged. shutdown and start-up (run1, run2 and tk/ss1, tk/ss2 pins) the two channels of the LTC3865/LTC3865-1 can be in- dependently shut down using the run1 and run2 pins. pulling either of these pins below 1.2v shuts down the main control loop for that controller. pulling both pins low disables both controllers and most internal circuits, including the intv cc regulator. releasing either run pin allows an internal 1a current to pull up the pin and enable that controller. alternatively, the run pin may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on this pin. the start-up of each controllers output voltage v out is controlled by the voltage on the tk/ss1 and tk/ss2 pins. when the voltage on the tk/ss pin is less than the 0.6v internal reference, the LTC3865 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6v reference. this allows the tk/ss pin to be used to program a soft- start by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.3a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0v to 0.6v (and beyond), the output voltage, v out , rises smoothly from zero to its fnal value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other sup- ply to ground (see the applications information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3.3v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off. light load current operation (burst mode operation, pulse-skipping or continuous conduction) the LTC3865/LTC3865-1 can be enabled to enter high effciency burst mode operation, constant-frequency pulse- skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin LTC3865/LTC3865-1 3865f pin to a dc voltage below 0.6v (e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, foat the mode/pllin pin. when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the average inductor current is higher than the load current, the error amplifer ea will decrease the voltage on the i th pin. when the i th voltage drops below 0.5v, the internal sleep signal goes high (enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the eas output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from revers- ing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor cur- rent is determined by the voltage on the i th pin, just as in normal operation. in this mode, the effciency at light loads is lower than in burst mode operation. however, continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the LTC3865 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse (discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current effciency than forced continuous mode, but not nearly as high as burst mode operation. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade-off between effciency and component size. low frequency opera- tion increases effciency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the LTC3865s controllers can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250khz to 770khz. there is a precision 7.5a current fow out of freq pin that user can program the controllers switching frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is integrated on the LTC3865 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. the pll loop flter network is integrated inside the LTC3865/LTC3865-1. the phase-locked loop is capable of locking any frequency within the range of 250khz to 770khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock. power good (pgood pins) on the LTC3865 (uh32 package), the pgood pin is bonded to the open drains of two individual internal n- channel mosfets. when either v osense voltage is not within 10% of the programmed voltage, the pgood pin is pulled low. the pgood pin is also pulled low when either run pin is below 1.2v or when the LTC3865 is in the soft-start or tracking phase. the pgood pin will fag power good immediately when both v osense are within the 10% of the programmed output voltage window. however, there is an internal 20s power bad mask when either v osense goes out the 10% window. the internal o pera t ion LTC3865/LTC3865-1 3865f power bad mask is 100s when there are any vid transi- tions. on the LTC3865 - 1 (uh32 package) or the LTC3865 (fe38 package), each channel has its own pgood pin. therefore, the pgood pins now only respond to their own channels. the pgood pins are allowed to be pulled up by external resistors to sources of up to 6v. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>10%) as well as other more serious condi- tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the reverse current limit for the overvoltage condition is reached. the bottom mosfet will be turned on again at the next clock and be turned off when the reverse current limit is reached again. this process repeats until the overvoltage condition is cleared. o pera t ion output voltage programming the output voltages of both channels of the LTC3865/ LTC3865-1 can be programmed to a preset value. there are two vid pins for each channel and by connecting these pins to intv cc , gnd, or by foating them, the output volt- ages can be set to the values in table 1. table 1. programming of output voltage vid11/vid21 vid12/vid22 v out1 /v out2 (v) intv cc intv cc 5.0 intv cc float 3.3 intv cc gnd 2.5 float intv cc 1.8 float float 0.6 or external divider float gnd 1.5 gnd intv cc 1.2 gnd float 1.0 gnd gnd 1.1 the typical application on the frst page is a basic LTC3865 application circuit. the LTC3865 can be confgured to use either dcr (inductor resistance) sensing or low value resis- tor sensing. the choice between the two current sensing schemes is largely a design trade-off between cost, power consumption and accuracy. dcr sensing is becoming popular because it saves expensive current sensing resis- tors and is more power effcient, especially in high current applications. however, current sensing resistors provide the most accurate current limits for the controller. other external component selection is driven by the load require- ment, and begins with the selection of r sense (if r sense is used) and inductor value. next, the power mosfets are se- lected. finally, input and output capacitors are selected. current limit programming the i lim pin is a tri-level logic input which sets the maxi- mum current limit of the controller. when i lim is either grounded, foated or tied to intv cc , the typical value for the maximum current sense threshold will be 30mv, 50mv or 75mv, respectively. a pplica t ions i n f or m a t ion which setting should be used? for the best current limit accuracy, use the 75mv setting. the 30mv setting will allow for the use of very low dcr inductors or sense resistors, but at the expense of current limit accuracy. the 50mv setting is a good balance between the two. for single output dual phase applications, use the 50mv or 75mv setting for optimal current sharing. sense + and sense C pins the sense + and sense C pins are the inputs to the current comparators. the common mode input voltage range of the current comparators is 0v to 5v. both sense pins are high impedance inputs with small base currents of less than 1a. when the sense pins ramp up from 0v to 1.4v, the small base currents fow out of the sense pins. when the sense pins ramp down from 5v to 1.1v, the small base currents fow into the sense pins. the high impedance inputs to the current comparators allow ac- curate dcr sensing. however, care must be taken not to foat these pins during normal operation. LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion filter components mutual to the sense lines should be placed close to the LTC3865/LTC3865-1, and the sense lines should run close together to a kelvin connection u n derneath the current sense element (shown in figure 1). sensing current elsewhere can effectively add parasitic inductance and capacitance to the current sense element, degrading the information at the sense terminals and mak- ing the programmed current limit unpredictable. if dcr sensing is used (figure 2b), sense resistor r1 should be placed close to the switching node, to prevent noise from coupling into sensitive small-signal nodes. the capacitor c1 should be placed close to the ic pins. c out to sense filter, next to the controller inductor or r sense 3865 f01 figure 1. sense lines placement with inductor or sense resistor for previous generation current mode controllers, the maximum sense voltage was high enough (e.g., 75mv for the ltc1628 / ltc3728 family) that the voltage drop across the parasitic inductance of the sense resistor represented a relatively small error. for todays highest current density solutions, however, the value of the sense resistor can be less than 1m? and the peak sense voltage can be as low as 20mv. in addition, inductor ripple currents greater than 50% with operation up to 1mhz are becoming more com- mon. under these conditions the voltage drop across the sense resistors parasitic inductance is no longer negligible. a typical sensing circuit using a discrete resistor is shown in figure 2a. in previous generations of controllers, a small rc flter placed near the ic was commonly used to reduce the effects of capacitive and inductive noise coupled in low value resistors current sensing a typical sensing circuit using a discrete resistor is shown in figure 2a. r sense is chosen based on the required output current. the current comparator has a maximum threshold v sense(max) determined by the i lim setting. the input common mode range of the current comparator is 0v to 5v. the current comparator threshold sets the peak of the inductor current, yielding a maximum average output current i max equal to the peak value less half the peak-to- peak ripple current, ?i l . to calculate the sense resistor value, use the equation: r v i i sense sense max max l = + ( ) ( ) ? 2 because of possible pcb noise in the current sensing loop, the ac current sensing ripple of ?v sense = ?i l ? r sense also needs to be checked in the design to get a good signal-to-noise ratio. in general, for a reasonably good pcb layout, a 15mv ?v sense voltage is recommended as a conservative number to start with, either for r sense or dcr sensing applications. v in v in intv cc boost tg sw bg pgnd filter components placed near sense pins sense + sense ? sgnd LTC3865 v out 3865 f02a c f ? 2 rf esl/r s pole-zero cancellation sense resistor plus parasitic inductance r s esl c f r f r f v in v in intv cc boost tg sw bg pgnd *place c1 near sense + , sense ? pins inductor dcrl sense + sense ? sgnd LTC3865 v out 3865 f02b r1 r2c1* r1 || r2 ? c1 = l dcr r sense(eq) = dcr r2 r1 + r2 (2a) using a resistor to sense current (2b) using the inductor dcr to sense current figure 2. two different methods of sensing current LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion the sense traces on the pcb. a typical flter consists of two series 10? resistors connected to a parallel 1000pf capacitor, resulting in a time constant of 20ns. this same rc flter, with minor modifcations, can be used to extract the resistive component of the current sense signal in the presence of parasitic inductance. for example, figure 3 illustrates the voltage waveform across a 2m? sense resistor with a 2010 footprint for the 1.2v/15a converter operating at 100% load. the waveform is the superposition of a purely resistive component and a purely inductive component. it was measured using two scope probes and waveform math to obtain a differential measurement. based on additional measurements of the inductor ripple current and the on-time and off-time of the top switch, the value of the parasitic inductance was determined to be 0.5nh using the equation: esl v i t t t t esl step l on off on off = ? + ( ) ? if the rc time constant is chosen to be close to the parasitic inductance divided by the sense resistor (l/r), the result- ing waveform looks resistive again, as shown in figure 4. for applications using low maximum sense voltages, check the sense resistor manufacturers data sheet for information about parasitic inductance. in the absence of data, measure the voltage drop directly across the sense resistor to extract the magnitude of the esl step and use the equation above to determine the esl. however, do not over flter. keep the rc time constant less than or equal to the inductor time constant to maintain a high enough ripple voltage on v rsense . the above generally applies to high density/high current applications where i (max) >10a and low values of induc- tors are used. for applications where i (max) < 10a, set r f to 10 and c f to 1000pf. this will provide a good starting point. the flter components need to be placed close to the ic. the positive and negative sense traces need to be routed as a differential pair and kelvin connected to the sense resistor. inductor dcr sensing for applications requiring the highest possible effciency at high load currents, the LTC3865/LTC3865-1 are capable of sensing the voltage drop across the inductor dcr, as shown in figure 2b. the dcr of the inductor represents the small amount of dc winding resistance of the copper, which can be less than 1m? for todays low value, high current inductors. in a high current application requiring such an inductor, conduction loss through a sense resis- tor would cost several points of effciency compared to dcr sensing. if the external r1||r2 ? c1 time constant is chosen to be exactly equal to the l/dcr time constant, the voltage drop across the external capacitor is equal to the drop across the inductor dcr multiplied by r2/(r1 + r2). r2 scales the voltage across the sense terminals for applications where the dcr is greater than the target sense resistor value. to properly dimension the external flter components, the dcr of the inductor must be known. it can be measured using a good rlc meter, but the dcr tolerance is not 500ns/div v sense 20mv/div 3865 f03 v esl(step) 500ns/div v sense 20mv/div 3865 f04 figure 3. voltage waveform measured directly across the sense resistor figure 4. voltage waveform measured after the sense resistor filter. c f = 1000pf, r f = 100 LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion always the same and varies with temperature; consult the manufacturers data sheets for detailed information. using the inductor ripple current value from the induc- tor value calculation section, the target sense resistor value is: r v i i sense equiv sense max max l ( ) ( ) ( ) = + ? 2 to ensure that the application will deliver full load current over the full operating temperature range, choose the minimum value for the maximum current sense threshold (v sense(max) ) in the electrical characteristics table (24mv, 44mv or 68mv, depending on the state of the i lim pin). next, determine the dcr of the inductor. where provided, use the manufacturers maximum value, usually given at 20c. increase this value to account for the temperature coeffcient of resistance, which is approximately 0.4%/c. a conservative value for t l(max) is 100c. to scale the maximum inductor dcr to the desired sense resistor value, use the divider ratio: r r dcr at t d sense equiv max l max = ( ) ( ) ( ) c1 is usually selected to be in the range of 0.047f to 0.47f. this forces r1||r2 to around 2k?, reducing error that might have been caused by the sense pins 1a current. the equivalent resistance r1||r2 is scaled to the room temperature inductance and maximum dcr: r r l dcr at c c 1 2 20 1 || ( ) ? = the sense resistor values are: r r r r r r r r d d d 1 1 2 2 1 1 = = ? || ; ? the maximum power loss in r1 is related to duty cycle, and will occur in continuous mode at the maximum input voltage: p r v v v r loss in max out out 1 1 = ? ( ) ( ) ? ensure that r1 has a power rating higher than this value. if high effciency is necessary at light loads, consider this power loss when deciding whether to use dcr sensing or sense resistors. light load power loss can be modestly higher with a dcr network than with a sense resistor, due to the extra switching losses incurred through r1. however, dcr sensing eliminates a sense resistor, reduces conduc- tion losses and provides higher effciency at heavy loads. peak effciency is about the same with either method. to maintain a good signal to noise ratio for the current sense signal, use a minimum ?v sense of 10mv to 15mv. for a dcr sensing application, the actual ripple voltage will be determined by the equation: ? = ? v v v r c v v f sense in out out in osc 1 1? ? slope compensation and inductor peak current slope compensation provides stability in constant- frequency architectures by preventing subharmonic oscil- lations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this results in a reduction of maximum inductor peak current for duty cycles >40%. however, the LTC3865/LTC3865-1 use a patented scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency f osc directly determine the inductors peak-to-peak ripple current: i v v v v f l ripple out in in out osc = ? ? ? ? ? ? ? ? LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest effciency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specifed maximum, the inductor should be chosen according to: l v v f i v v in out osc ripple out in ? ? ? inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fxed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will increase. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can con- centrate on copper loss and preventing saturation. ferrite core material saturates hard, which means that induc- tance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection two external power mosfets must be selected for each controller in the LTC3865/LTC3865-1: one n-channel mosfet for the top (main) switch, and one n-channel mosfet for the bottom (synchronous) switch. the peak-to-peak drive levels are set by the intv cc voltage. this voltage is typically 5v during start-up (see extv cc pin connection). consequently, logic-level threshold mosfets must be used in most applications. the only exception is if low input voltage is expected (v in < 5v); then, sub-logic level threshold mosfets (v gs(th) < 3v) should be used. pay close attention to the bv dss specifcation for the mosfets as well; most of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on- resistance, r ds(on) , miller capacitance, c miller , input voltage and maximum output current. miller capacitance, c miller , can be approximated from the gate charge curve usually provided on the mosfet manufacturers data sheet. c miller is equal to the increase in gate charge along the horizontal axis while the curve is approximately fat divided by the specifed change in v ds . this result is then multiplied by the ratio of the application applied v ds to the gate charge curve specifed v ds . when the ic is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: main switch duty cycle v v synchronous switc out in = hh duty cycle v v v in out in = ? the mosfet power dissipations at maximum output current are given by: p v v i r v i main out in max ds on in max = ( ) + ( ) + ( ) 2 2 1 d ( ) 22 1 1 ? ? ? ? ? ? ( )( ) + r c v v v dr miller intvcc th min ? ? ( ) tth min osc sync in out in max f p v v v i ( ) ? ? ? ? ? ? ? ? ? ? = ( )) + ( ) 2 1 d r ds on( ) where d is the temperature dependency of r ds(on) and r dr (approximately 2?) is the effective driver resistance at the mosfets miller threshold voltage. v th(min) is the typical mosfet minimum threshold voltage. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion which are highest at high input voltages. for v in < 20v the high current effciency generally improves with larger mosfets, while for v in > 20v the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher effciency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + d ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but d = 0.005/c can be used as an approximation for low voltage mosfets. the optional schottky diodes conduct during the dead time between the conduction of the two power mosfets. these prevent the body diodes of the bottom mosfets from turn- ing on, storing charge during the dead time and requiring a reverse recovery period that could cost as much as 3% in effciency at high v in . a 1a to 3a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition losses due to their larger junction capacitance. soft-start and tracking the LTC3865/LTC3865-1 have the ability to either soft-start by themselves with a capacitor or track the output of another channel or external supply. when one particular channel is confgured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.2v. its tk/ss pin is actively pulled to ground in this shutdown state. once the run pin voltage is above 1.2v, the channel pow- ers up. a soft-start current of 1.3a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current foldback is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defned to be the voltage range from 0v to 0.6v on the tk/ss pin. the total soft-start time can be calculated as: t c a softstart ss = 0 6 1 3 . ? . regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.5v. between tk/ss = 0.5v and 0.54v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.54v. the output ripple is minimized during the 40mv forced continuous mode window ensuring a clean pgood signal. when the channel is confgured to track another supply, the feedback voltage of the other supply is duplicated by a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always fowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the LTC3865/LTC3865-1 are forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.54v regardless of the setting on the mode/pllin pin. however, the LTC3865/LTC3865-1 should always be set in force con- tinuous mode tracking down when there is no load. after tk/ss drops below 0.1v, the corresponding channel will operate in discontinuous mode. output voltage tracking the LTC3865/LTC3865-1 allow the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either co- incidentally or ratiometrically track another supplys output, as shown in figure 5. in the following discussions, v out1 refers to the LTC3865/LTC3865-1s output 1 as a master channel and v out2 refers to the LTC3865/LTC3865 - 1s out- put 2 as a slave channel. in practice, though, either phase can be used as the master. to implement the coincident tracking in figure 5a, connect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels internal feedback divider LTC3865/LTC3865-1 0 3865f a pplica t ions i n f or m a t ion shown in figure 6a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking, the ratio of the v out2 divider should be exactly the same as the master channels internal feedback divider. by selecting different resistors, the LTC3865/LTC3865-1 can achieve different modes of tracking including the two in figure 5. so which mode should be programmed? the coincident mode offers better output regulation. this can be better understood with the help of figure 7. at the input stage of the slave channels error amplifer, two common an- ode diodes are used to clamp the equivalent reference voltage and an additional diode is used to match the shifted common mode voltage. the top two current sources are of the same magnitude. in coincident mode, the tk/ss voltage is substantially higher than 0.6v at steady state and effectively turns off d1. d2 and d3 will therefore conduct the same current and offer tight matching between v fb2 and the internal precision 0.6v at steady state. in the ratiometric mode, however, tk/ss equals 0.6v at steady state. d1 will divert part of the bias current to make v fb2 slightly lower than 0.6v. although this error is minimized by the exponential i-v characteristics of the diode, it does impose a fnite amount of output voltage deviation. time (5a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 3865 f05 (5b) ratiometric tracking output voltage figure 5. two different modes of output voltage tracking nr3 r1 nr4 r2 r3 v out2 r4 (6a) coincident tracking setup to ea1 to tk/ss2 pin to ea2 v out1 38551 f06 (6b) ratiometric tracking setup nr1 r1 nr2 r2 r3 v out2 r4 to ea1 to tk/ss2 pin to ea2 v out1 figure 6. setup for coincident and ratiometric tracking ? + d3 3865 f07 d2 d1 tk/ss2 0.6v v fb2 i i ea2 figure 7. equivalent input circuit of error amplifer LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion when the master channels output experiences dynamic excursion (under load transient, for example), the slave channel output will be affected as well. for better output regulation, use the coincident tracking mode instead of ratiometric. intv cc regulators and extv cc the LTC3865 features a true pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the LTC3865/LTC3865-1s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5v when v in is greater than 5.5v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7v. each of these can supply a peak current of 80ma and must be bypassed to ground with a minimum of 4.7f ceramic capacitor or low esr electrolytic capacitor. no mat- ter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maximum junction temperature rating for the LTC3865/LTC3865-1 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7v, the linear regulator is enabled. power dissipation for the ic in this case is highest and is equal to v in ? i intvcc . the gate charge current is depen- dent on operating frequency as discussed in the effciency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the LTC3865 intv cc current is limited to less than 42ma from a 38v supply in the uh package and not using the extv cc supply: t j = 70c + (42ma)(38v)(34c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = sgnd) at maximum v in . when the voltage applied to extv cc rises above 4.7v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5v. using the extv cc allows the mosfet driver and control power to be derived from one of the LTC3865/LTC3865-1s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation (e.g., start-up, short-circuit). if more current is required through the extv cc than is speci- fed, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6v to the extv cc pin and make sure that extv cc < v in . signifcant effciency and thermal gains can be realized by powering intv cc from the output, since the v in current resulting from the driver and control currents will be scaled by a factor of (duty cycle)/(switcher effciency). tying the extv cc pin to a 5v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (42ma)(5v)(34c/w) = 77c however, for 3.3v and other low voltage outputs, addi- tional circuitry is required to derive intv cc power from the output. the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open (or grounded). this will cause intv cc to be powered from the internal 5v regulator result- ing in an effciency penalty of up to 10% at high input voltages. 2. ext v cc connected directly to v out . this is the normal connection for a 5v regulator and provides the highest effciency. 3. e xtv cc connected to an external supply. if a 5v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. e xtv cc connected to an output-derived boost network. for 3.3v and other low voltage regulators, effciency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion for applications where the main input power is below 5v, tie the v in and intv cc pins together and tie the combined pins to the 5v input with a 1? or 2.2? resistor as shown in figure 8 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the intv cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic-level devices. topside mosfet driver supply (c b , d b ) external bootstrap capacitors, c b , connected to the boost pins supply the gate drive voltages for the topside mosfets. capacitor c b in the functional diagram is charged through external diode d b from intv cc when the sw pin is low. when one of the topside mosfets is to be turned on, the driver places the c b voltage across the gate source of the desired mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc . the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet(s). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the fnal arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the effciency has improved. if there is no change in input current, then there is no change in effciency. undervoltage lockout the LTC3865/LTC3865-1 have two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.3v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 550mv of precision hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn-on reference of 1.2v, one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5a of current fows out of the run pin once the run pin voltage passes 1.2v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.5v. c in and c out selection the selection of c in is simplifed by the 2-phase architec- ture and its impact on the worst-case rms current drawn through the input network (battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current occurs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used in the formula below to determine the maximum rms capacitor current requirement. increasing the output current drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of- phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the intv cc LTC3865 r vin 1 c in 3865 f08 c intvcc 4.7f 5v + v in figure 8. setup for a 5v input LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c quired i i v v v v in rms max in out in out re ? ( )( ) ? ? ? ?? 1 2/ this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even signifcant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci- tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the LTC3865, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the beneft of the LTC3865/LTC3865-1 2-phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement calculated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall beneft of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the effciency testing. the sources of the top mosfets should be placed within 1cm of each other and share a common c in (s). separating the sources and c in may produce undesirable voltage and current resonances at v in . a small (0.1f to 1f) bypass capacitor between the chip v in pin and ground, placed close to the LTC3865/LTC3865-1, is also suggested. a 2.2? to 10? resistor placed between c in (c1) and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance (esr). typically, once the esr requirement is satisfed, the capacitance is adequate for fltering. the output ripple (?v out ) is approximated by: ? + ? ? ? ? ? ? v i esr fc out ripple out 1 8 where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the LTC3865/LTC3865-1 output voltages are each set by the voltages at vid pins. each of the vid pins can be foated, or intv cc or grounded, depending on what preset voltages are needed at the output (table 1). if the desired output voltage is not one of the preset values, select 0.6v and use 1% resistors to divide v out , as shown in figure 9. the regulated output voltage is determined by: v v r r out b a = + ? ? ? ? ? ? 0 6 1. ? to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v osense line away from noise sources, such as the inductor or the sw line. v osense v out r b r a c ff 1/2 LTC3865 3865 f09 figure 9. setting output voltage LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion fault conditions: current limit and current foldback the LTC3865/LTC3865-1 include current foldback to help limit load current when the output is shorted to ground. if the output falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one-third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions with very low duty cycles, the LTC3865 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short-circuit ripple current is determined by the minimum on-time t on(min) of the LTC3865/LTC3865-1 ( 90ns), the input voltage and inductor value: ? i t v l l sc on min in ( ) ( ) ? = the resulting short-circuit current is: i v r i sc sense max sense l sc = 1 3 1 2 / ? ( ) ( ) ? phase-locked loop and frequency synchronization the LTC3865/LTC3865-1 have a phase-locked loop (pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2s top mosfet is thus 180 degrees out-of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal flter network. there is a precision 7.5a of current fowing out of freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/pllin pin. the internal switch between freq pin and the integrated pll flter network is on, allowing the flter network to be at the same voltage potential as of freq pin. the relationship between the volt- age on the freq pin and the operating frequency is shown in figure 10 and specifed in the electrical characteristic table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above will turn off and isolate the infuence of freq pin. note that the LTC3865 can only be synchronized to an external clock whose frequency is within range of the LTC3865/LTC3865-1s internal v co . this is guaranteed to be between 250khz and 770khz. a simplifed block diagram is shown in figure 11. freq pin voltage (v) 0 frequency (khz) 0.5 1 1.5 2 3865 f10 2.5 0 100 300 400 500 900 800 700 200 600 digital phase/ frequency detector sync vco 2.4v 5v 7.5a r set 3865 f11 freq external oscillator mode/ pllin figure 10. relationship between oscillator frequency and voltage at the freq pin figure 11. phase-locked loop block diagram LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion if the external clock frequency is greater than the inter- nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the flter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the flter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to the phase difference. the voltage on the flter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the flter capacitor holds the voltage. typically, the external clock (on mode/pllin pin) input high threshold is 1.6v, while the input low thres-hold is 1v. the external clock should not be applied when the ic is in shutdown. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the LTC3865/LTC3865-1 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that t v v on min out in ( ) ( ) < f if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the LTC3865/LTC3865-1 is approximately 90ns, with reasonably good pcb layout, minimum 30% inductor current ripple and at least 10mv to 15mv ripple on the current sense signal. the mini- mum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 130ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a signifcant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. effciency considerations the percent effciency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the effciency and which change would produce the most improvement. percent effciency can be expressed as: %effciency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent- age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in LTC3865/LTC3865-1 circuits: 1) ic v in current, 2) intv cc regulator current, 3) i 2 r losses, 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typi- cally results in a small (<0.1%) loss. 2. int v cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(q t + q b ), where q t and q b are the gate charges of the topside and bottom side mosfets. LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion supplying intv cc power through extv cc from an output-derived source will scale the v in current re- quired for the driver and control circuits by a factor of (duty cycle)/(effciency). for example, in a 20v to 5v application, 10ma of intv cc current results in approximately 2.5ma of v in current. this reduces the mid-current loss from 10% or more (if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse (if used), mosfet, inductor, current sense resistor. in continuous mode, the average output current fows through l and r sense , but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l and r sense to ob- tain i 2 r losses. for example, if each r ds(on) = 10m?, r l = 10m?, r sense = 5m?, then the total resistance is 25m?. this results in losses ranging from 2% to 8% as the output current increases from 3a to 15a for a 5v output, or a 3% to 12% loss for a 3.3v output. effciency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. t ransition losses apply only to the topside mosfet(s), and become signifcant only when operating at high input voltages (typically 15v or greater). transition losses can be estimated from: t ransition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional 5% to 10% effciency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. a 25w supply will typically require a minimum of 20f to 40f of capacitance having a max- imum of 20m? to 50m? of esr. the LTC3865 2-phase architecture typically halves this input capacitance require- ment over competing solutions. other losses including schottky conduction losses during dead time and induc- tor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr), where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc coupled and ac fltered closed loop response test point. the dc step, rise time and settling at this test point truly refects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion the i th series r c -c c flter sets the dominant pole-zero loop compensation. the values can be modifed slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the fnal pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1s to 10s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without break- ing the feedback loop. placing a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the fltered and compensated control loop response. the gain of the loop will be in- creased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10f capacitor would require a 250s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 12. figure 13 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n-channel mosfets m1 and m3 located within 1 cm of each other with a common drain con- nection at c in ? do not attempt to split the input de- coupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) ter- minals. the v osense and i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. d o the LTC3865 v osense pins connect to the (+) terminals of c out ? the connections between the v osense pins and c out should not be along the high current input feeds from the input capacitor(s). 4. are the sense + and sense C leads routed together with minimum pc trace spacing? the flter capacitor between sense + and sense C should be as close as possible to the ic. ensure accurate current sensing with kelvin connections at the sense resistor or inductor, whichever is used for current sensing. 5. is the intv cc decoupling capacitor connected close to the ic, between the intv cc and the power ground pins? this capacitor carries the mosfet drivers current peaks. an additional 1f ceramic capacitor placed immediately next to the intv cc and pgnd pins can help improve noise performance substantially. LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion c b2 c b1 c intvcc + c in d1 ceramic m1 m2 m3 m4 d2 + c vin v in r in l1 l2 c out1 v out1 gnd v out2 3865 f12 + c out2 + r sense r sense r pu2 pgood v pull-up f in ceramic i th1 v osense1 sense1 + sense1 ? freq sense2 ? sense2 + v osense2 i th2 tk/ss2 tk/ss1 pgood sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 sgnd i lim mode/pllin run1 run2 vid11 LTC3865 vid22 tg1 vid21 vid12 figure 12. recommended printed circuit layout diagram r l1 d1 l1 sw1 r sense1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3865 f13 r sense2 v out2 c out2 figure 13. branch current waveforms LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion 6. keep the switching nodes (sw1, sw2), top gate nodes (tg1, tg2), and boost nodes (boost1, boost2) away from sensitive small-signal nodes, especially from the opposite channels voltage and current sensing feed- back pins. all of these nodes have very large and fast moving signals and therefore should be kept on the output side of the LTC3865/LTC3865-1 and occupy minimum pc trace area. if dcr sensing is used, place the top resistor (figure 2b, r1) close to the switching node. 7. use a modifed star ground technique: a low imped- ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intv cc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node (sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be main- tained over the input voltage range down to dropout and until the output load drops below the low current opera- tion thresholdtypically 10% of the maximum designed current level in burst mode operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implemen- tation. variation in the duty cycle at a subharmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensation. overcompensa- tion of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly diffcult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the undervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out- put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition, investigate common ground path voltage pickup between these components and the sgnd pin of the ic. LTC3865/LTC3865-1 0 3865f a pplica t ions i n f or m a t ion d3 d4 m1 0.1f l1 3.3h 3.65k 1% 1800pf 100pf 0.1f 0.1f 22f 50v c out1 100f s2 l1, l2: coiltronics hcp0703 m1, m2: vishay siliconix si4816bdy c out1 , c out2 : taiyo yuden jmk325bj107mm 4.75k 1% v out1 3.3v 5a m2 0.1f l2 2.2h 1.58k 1% 2200pf 100pf c out2 100f s2 5.49k 1% 162k 1% v out2 1.8v 5a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + vid21 sense1 ? sense2 ? v osense1 v osense2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 20v 3865 f14 extv cc 0.1f 0.1f LTC3865 mode/pllin i lim run2 run1 vid22 vid12 vid11 5.49k 1% 1.37k 1% 4.7f 1f 2.2 + figure 14. high effciency dual 500khz 3.3v/1.8v step-down converter design example as a design example for a 2-channel medium cur- rent regulator, assume v in = 12v (nominal), v in = 20v (maximum), v out1 = 3.3v, v out2 = 1.8v, i max1,2 = 5a, and f = 500khz (see figure 14). the regulated output voltages are set by connecting vid11 and vid22 to intv cc and foating vid12 and vid21. the frequency is set by biasing the freq pin to 1.2v (see figure 9). the inductance values are based on a 35% maximum ripple current assumption (1.75a for each channel). the highest value of ripple current occurs at the maximum input voltage: l v i v v out l max out in max = ? ? ? ? ? ? ? f ? ( ) ( ) ? 1 channel 1 will require 3.2h, and channel 2 will require 1.9h. the next highest standard values are 3.3h and 2.2h. at the nominal input voltage (12v), the ripple will be: ? i v l v v l nom out out in nom ( ) ( ) ? = ? ? ? ? ? ? ? f 1 channel 1 will have 1.45a (29%) ripple, and channel 2 will have 1.4a (28%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 5.725a for channel 1 and 5.7a for channel 2. the minimum on-time occurs on channel 1 at the maximum v in , and should not be less than 90ns: t v v v v khz n on min out in max ( ) ( ) . ( ) = = = f 1 8 20 500 180 ss LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion with i lim foating, the equivalent r sense resistor value can be calculated by using the minimum value for the maximum current sense threshold (44mv). r v i i sense equiv sense min load max l nom ( ) ( ) ( ) ( = + ? )) . . 2 44 5 1 5 2 7 7 = + @ mv a a m ? the equivalent r sense is the same for channel 2. the coiltronics (cooper) hcp0703-2r2 (20m dcr max at 20c) and hcp0703-3r3 (30m? dcr max at 20c) are chosen. at 100c, the estimated maximum dcr values are 26.4m? and 39.6m?. the divider ratios are: r r dcr at t m m d sense equiv max l max = = ( ) ( ) . . 7 7 26 4 ? ? == @ 0 3 7 7 39 6 0 2 . ; . . . and m m ? ? for each channel, 0.1f is selected for c1. r r l dcr at c c h m f max 1 2 20 1 2 2 20 0 1 1 || ( ) ? . ? . = = = ? .. ; . ? . . 1 3 3 30 0 1 1 1 k and h m f k ? = for channel 1, the dcr sense flter/divider values are: r r r r k k r r r r k d d d 1 1 2 1 1 0 2 5 5 2 1 1 5 5 = = @ = ? = || . . . ; ? . ? 00 2 1 0 2 1 37 . . . ? @ k the power loss in r1 at the maximum input voltage is: p r v v v r v v loss in max out out 1 1 20 3 3 3 = ? = ? ( ) ? ( . ) ? ( ) .. . 3 5 5 10 v k mw = the respective values for channel 2 are r1 = 3.66k, r2 = 1.57k; and p loss r1 = 8mw. burst mode operation is chosen for high light load effciency (figure 15) by foating the mode/pllin pin. power loss due to the dcr sensing network is slightly higher at light loads than would have been the case with a suitable sense resistor (8m?). at heavier loads, dcr sensing provides higher effciency. the power dissipation on the topside mosfet can be easily estimated. choosing a siliconix si4816bdy dual mosfet results in: r ds(on) = 0.023?/0.016?, c miller @ 100pf. at maximum input voltage with t(estimated) = 50c: p v v c c main = ( ) + [ ] 3 3 20 5 1 0 005 50 25 0 0 2 . ( . )( ? ) ? . 223 20 5 2 2 100 1 5 2 3 1 2 2 ? ( ) + ( ) ? ? ? ? ? ? ? ( )( ) + v a pf ? ? . ..3 500 186 ? ? ? ? ? ? ( ) = khz mw load current (ma) 0.01 70 efficiency (%) power loss (mw) 80 90 0.1 1 10 60 50 40 100 0.1 1 0.01 10 3865 f16 dcr 8m power loss efficiency figure 15. design example effciency vs load LTC3865/LTC3865-1 3865f a pplica t ions i n f or m a t ion a short-circuit to ground will result in a folded back cur- rent of: i mv ns v h sc = ( ) ? ? ? ? ? ? ? = 1 3 50 0 008 1 2 90 20 3 3 / . ? ( ) . 11 8. a with a typical value of r ds(on) and d = (0.005/c)(20) = 0.1. the resulting power dissipated in the bottom mosfet is: p v v v a m sync = ( ) ( ) ? ( ) = 20 3 3 20 1 8 1 125 0 016 48 2 ? . . . . ww which is less than under full-load conditions. c in is chosen for an rms current rating of at least 2a at temperature assuming only channel 1 or 2 is on. c out is chosen with an esr of 0.02? for low output ripple. the output ripple in continuous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.02?(1.5a) = 30mv p-p 0.1f l2 0.47h q1 rjk0305dpb q3 rjk0305dpb q4 rjk0330dpb d2 q2 rjk0330dpb 1000pf 1000pf 1000pf 22f 50v 10k v out1 1.5v 15a 0.1f l2 0.47h 1000pf c out4 100f 15k 162k 1% v out2 1.2v 15a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + run2 sense1 ? sense2 ? v osense1 v osense2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 4.5v to 24v 3865 f16 0.1f 100pf 0.1f LTC3865 10f 35v 10f 35v mode/pllin i lim run1 vid11 vid12 vid21 vid22 extv cc 4.7f c out1 100f c out2,3 100pf 100 100 100 100 2.2 1f d4 d3 d1, d2: vishay b340a l1, l2: vishay ihlp4040dzerr47m11 c out1 , c out4 : tdk c322jx5r0j107mt c out2 , c out3 , c out5 , c out6 : sanyo 4tpe 220f 2m 2m + c out5,6 + + d1 figure 16. 1.5v/15a, 1.2v/15a converter using sense resistors t ypical applica t ions LTC3865/LTC3865-1 3865f t ypical applica t ions figure 17. high v in , 3.6v/10a, 2v/10a converter with external sense resistors synchronized at 400khz d3 cmdsh-3 d4 cmdsh-3 0.1f hat2266h hat2266h l1 2.2h pllin 400khz 0.004 hat2266h hat2266h 1800pf 100pf 1nf 1nf c in1 22f 50v c out1 220f s2 c out1 , c out2 : sanyo 4tpe 220f l1: toko fda1055-2r2m l2: toko fd1055-1r2m 50k 1% 100 100 17.8k 1% 10k 1% v out1 3.6v 10a 0.1f l2 1.2h 0.004 2200pf 100pf c out2 220f s2 14.7k 1% 10k 1% v out2 2v 10a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + vid21 sense1 ? sense2 ? v osense1 v osense2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 36v 3865 f17 extv cc 0.1f 0.1f 121k LTC3865 3.3f 50v 3.3f 50v mode/pllin i lim run2 run1 vid22 vid12 vid11 100 100 23.2k 1% 4.7f c in2 1f 2.2 + + + d3 d4 0.1f rjk0305dpb rjk0330dpb rjk0330dpb l1 0.47h 6800pf 100pf 0.1f 0.1f 162k run1 run2 0 22f 50v c out1 220f c out1 , c out2 : sanyo 4tpe 220f l1, l2: vishay ihlp4040dzerr47m11 100 100 1.21k 1% 2m 0.1f l2 0.47h c out2 220f 1.2v 30a tg1 tg2 boost1 boost2 sw1 sw2 bg1 bg2 sgnd pgnd freq sense1 + sense2 + vid21 sense1 ? sense2 ? v osense1 v osense2 i th1 i th2 v in pgood intv cc tk/ss1 tk/ss2 v in 7v to 20v 3865 f18 extv cc 0.1f LTC3865 mode/pllin i lim run2 run1 vid22 vid12 vid11 2m 100 100 4.7f 1f 2.2 + + + rjk0305dpb 10f 35v 10f 35v figure 18. high current, single output, 1.2v/30a converter using sense resistors LTC3865/LTC3865-1 3865f p ackage descrip t ion uh package 32-lead plastic qfn (5mm 5mm) (reference ltc dwg # 05-08-1693 rev d) 5.00 p 0.10 (4 sides) note: 1. drawing proposed to be a jedec package outline m0-220 variation whhd-(x) (to be approved) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 p 0.10 31 1 2 32 bottom view?exposed pad 3.50 ref (4-sides) 3.45 p 0.10 3.45 p 0.10 0.75 p 0.05 r = 0.115 typ 0.25 p 0.05 (uh32) qfn 0406 rev d 0.50 bsc 0.200 ref 0.00 ? 0.05 0.70 p0.05 3.50 ref (4 sides) 4.10 p0.05 5.50 p0.05 0.25 p 0.05 package outline 0.50 bsc recommended solder pad layout apply solder mask to areas that are not soldered pin 1 notch r = 0.30 typ or 0.35 s 45 o chamfer r = 0.05 typ 3.45 p 0.05 3.45 p 0.05 LTC3865/LTC3865-1 3865f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion fe package 38-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1772 rev a) exposed pad variation aa 4.75 (.187) ref fe38 (aa) tssop 0608 rev a 0.09 ? 0.20 (.0035 ? .0079) 0 o ? 8 o 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 19 20 ref 9.60 ? 9.80* (.378 ? .386) 38 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.50 (.0196) bsc 0.17 ? 0.27 (.0067 ? .0106) typ recommended solder pad layout 0.315 0.05 0.50 bsc 4.50 ref 6.60 0.10 1.05 0.10 4.75 ref 2.74 ref 2.74 (.108) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc LTC3865/LTC3865-1 3865f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0210 ? printed in usa r ela t e d p ar t s part number description comments ltc3850/ltc3850-1 ltc3850-2 dual 2-phase, high effciency synchronous step-down dc/dc controllers, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 780khz, 4v v in 30v, 0.8v v out 5.25v ltc3855 dual, multiphase synchronous step-down dc/dc controller with diffamp and dcr temperature compensation phase-lockable fixed operating frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12.5v ltm ? 4619 dual, 4a dc/dc module ? complete power supply high effciency, compact size, fast transient response 4.5v v in 26.5v, 0.8v v out 5v, 15mm 15mm 2.8mm lga ltc3868/ltc3868-1 low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle phase-lockable fixed operating frequency 50khz to 900khz, 4v v in 24v, 0.8v v out 14v, i q = 170a, ltc3857/ltc3857-1 low i q , dual, 2-phase synchronous step-down controllers 50a i q , 0.8v v out 24v, 4v v in 38v, output overcurrent foldback protection ltc3858/ltc3858-1 low i q , dual, 2-phase synchronous step-down controllers 170a i q , 0.8v v out 24v, 4v v in 38v, output overcurrent latchoff protection ltc3853 triple output, multiphase synchronous step-down dc/dc controller, r sense or dcr current sensing and tracking phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 24v, v out up to 13.5v ltc3854 small footprint wide v in range synchronous step-down dc/dc controller fixed 400khz operating frequency 4.5v v in 38v, 0.8v v out 5.25v, 2mm 3mm qfn-12 ltc3851a ltc3851a-1 no r sense ? wide v in range synchronous step-down dc/dc controller phase-lockable fixed operating frequency 250khz to 750khz, 4v v in 38v, 0.8v v out 5.25v, msop-16e, 3mm 3mm qfn-16, ssop-16 ltc3775 high frequency, synchronous voltage mode step-down dc/dc controller synchronizable fixed frequency 250khz to 1mhz, t on(min) = 30ns, 4v v in 38v, 0.6v v out 0.8v, msop-16e, 3mm 3mm qfn-16 ltc3878 no r sense constant on-time synchronous step-down dc/dc controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.8v v out 0.9v in , ssop-16 ltc3879 no r sense constant on-time synchronous step-down dc/dc controller very fast transient response, t on(min) = 43ns, 4v v in 38v, 0.6v v out 0.9v in , msop-16e, 3mm 3mm qfn-16 ltm4600hv 10a dc/dc module regulator high effciency, compact size, fast transient response 4.5v v in 28v, 0.8v v out 5v, 15mm 15mm 2.8mm lga ltm4601ahv 12a dc/dc module regulator high effciency, compact size, fast transient response 4.5v v in 28v, 0.8v v out 5v, 15mm 15mm 2.8mm lga ltc3610 12a, 1mhz, monolithic synchronous step-down dc/dc converter high effciency, adjustable constant on-time 4v v in 24v, v out(min) 0.6v, 9mm 9mm qfn-64 ltc3611 10a, 1mhz, monolithic synchronous step-down dc/dc converter high effciency, adjustable constant on-time 4v v in 32v, v out(min) 0.6v, 9mm 9mm qfn-64 |
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